339 search results - page 35 / 68 » Hardware Synthesis for Multi-Dimensional Time |
118
Voted
IESS
2007
Springer
15 years 6 months ago
2007
Springer
: The performance of feasibility tests is crucial in many applications. When using feasibility tests online only a limited amount of analysis time is available. Run-time efficiency...
ICCAD
2007
IEEE
2007
IEEE
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design
15 years 9 months ago
—Register allocation, in high-level synthesis and ASIP design, is the process of determining the number of registers to include in the resulting circuit or processor. The goal is...
90
Voted
ICCAD
2002
IEEE
15 years 9 months ago
2002
IEEE
Embedded system programs tend to spend much time in small loops. Introducing a very small loop cache into the instruction memory hierarchy has thus been shown to substantially red...
70
Voted
DATE
1998
IEEE
15 years 4 months ago
1998
IEEE
In this paper, we present an approach to synthesize multiple behavior modules. Given n DFGs to be implemented, the previous methods scheduled each of them sequentially, and implem...
103
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ISCA
1997
IEEE
15 years 4 months ago
1997
IEEE
As processor architectures have increased their reliance on speculative execution to improve performance, the importance of accurate prediction of what to execute speculatively ha...