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EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
15 years 1 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
ASAP
2007
IEEE
123views Hardware» more  ASAP 2007»
15 years 4 months ago
A memcpy Hardware Accelerator Solution for Non Cache-line Aligned Copies
In this paper, we present a hardware solution to perform non cache-line aligned memory copies allowing the commonly used memcpy function to cope with word copies. The main purpose...
Filipa Duarte, Stephan Wong
PPOPP
2006
ACM
15 years 3 months ago
Exploiting distributed version concurrency in a transactional memory cluster
We investigate a transactional memory runtime system providing scaling and strong consistency for generic C++ and SQL applications on commodity clusters. We introduce a novel page...
Kaloian Manassiev, Madalin Mihailescu, Cristiana A...
FPL
2010
Springer
155views Hardware» more  FPL 2010»
14 years 7 months ago
Design and Implementation of Real-Time Transactional Memory
Transactional memory is a promising, optimistic synchronization mechanism for chip-multiprocessor systems. The simplicity of atomic sections, instead of using explicit locks, is al...
Martin Schoeberl, Peter Hilber
ISCA
2007
IEEE
174views Hardware» more  ISCA 2007»
15 years 3 months ago
An integrated hardware-software approach to flexible transactional memory
There has been considerable recent interest in the support of transactional memory (TM) in both hardware and software. We present an intermediate approach, in which hardware is us...
Arrvindh Shriraman, Michael F. Spear, Hemayet Hoss...