286 search results - page 20 / 58 » Hardware acceleration of transactional memory on commodity s... |
125
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IEEEPACT
2006
IEEE
15 years 7 months ago
2006
IEEE
Transactional memory is an attractive design concept for scalable multiprocessors because it offers efficient lock-free synchronization and greatly simplifies parallel software....
129
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IPPS
2010
IEEE
14 years 10 months ago
2010
IEEE
We present a novel architecture of a communication engine for non-coherent distributed shared memory systems. The shared memory is composed by a set of nodes exporting their memory...
125
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ACMMSP
2006
ACM
15 years 7 months ago
2006
ACM
Open nesting provides a loophole in the strict model of atomic transactions. Moss and Hosking suggested adapting open nesting for transactional memory, and Moss and a group at Sta...
154
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SIGOPS
2010
14 years 8 months ago
2010
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
124
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IPPS
2007
IEEE
15 years 7 months ago
2007
IEEE
At the core of contemporary high performance computer systems is the communication infrastructure. For this reason, there has been a lot of work on providing low-latency, high-ban...