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DATE
2003
IEEE
132views Hardware» more  DATE 2003»
15 years 2 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...
GIS
2006
ACM
14 years 9 months ago
Dynamic simplification and visualization of large maps
In this paper, we present an algorithm that performs simplification of large geographical maps through a novel use of graphics hardware. Given a map as a collection of non-interse...
Nabil H. Mustafa, Shankar Krishnan, Gokul Varadhan...
SIGMETRICS
2006
ACM
174views Hardware» more  SIGMETRICS 2006»
15 years 3 months ago
Understanding the management of client perceived response time
Understanding and managing the response time of web services is of key importance as dependence on the World Wide Web continues to grow. We present Remote Latency-based Management...
David P. Olshefski, Jason Nieh
VIS
2005
IEEE
165views Visualization» more  VIS 2005»
15 years 10 months ago
High Dynamic Range Volume Visualization
High resolution volumes require high precision compositing to preserve detailed structures. This is even more desirable for volumes with high dynamic range values. After the high ...
Baoquan Chen, David H. Porter, Minh X. Nguyen, Xia...
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
13 years 10 hour ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar