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ISCA
2012
IEEE
281views Hardware» more  ISCA 2012»
13 years 10 hour ago
LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems
Memory system reliability is a serious and growing concern in modern servers. Existing chipkill-level memory protection mechanisms suffer from several drawbacks. They activate a l...
Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev B...
GRAPHICSINTERFACE
2003
14 years 11 months ago
Hardware-Accelerated Visual Hull Reconstruction and Rendering
We present a novel algorithm for simultaneous visual hull reconstruction and rendering by exploiting off-theshelf graphics hardware. The reconstruction is accomplished by projecti...
Ming Li, Marcus A. Magnor, Hans-Peter Seidel
ASPLOS
2011
ACM
14 years 1 months ago
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such a...
Luke Dalessandro, François Carouge, Sean Wh...
ISCA
2007
IEEE
143views Hardware» more  ISCA 2007»
15 years 3 months ago
Performance pathologies in hardware transactional memory
Hardware Transactional Memory (HTM) systems reflect choices from three key design dimensions: conflict detection, version management, and conflict resolution. Previously propos...
Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Y...
IEEEPACT
2008
IEEE
15 years 4 months ago
Scalable and reliable communication for hardware transactional memory
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen ...