951 search results - page 43 / 191 » Hardware design experiences in ZebraNet |
103
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DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
— This paper introduces a graph grammar based approach to automated topology synthesis of analog circuits. A grammar is developed to generate circuits through production rules, t...
ISQED
2003
IEEE
15 years 5 months ago
2003
IEEE
- This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a cha...
117
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FPL
2000
Springer
15 years 3 months ago
2000
Springer
This paper discusses the design and implementation of finite state machines (FSM) with combinational circuits that are built primarily from RAM blocks. It suggests a novel state as...
106
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ASAP
2008
IEEE
15 years 1 months ago
2008
IEEE
Automatic generation of custom instruction processors from high-level application descriptions enables fast design space exploration, while offering very favorable performance and...
DATE
2005
IEEE
15 years 5 months ago
2005
IEEE
In this paper we present an approach to the design optimization of faulttolerant embedded systems for safety-critical applications. Processes are statically scheduled and communic...