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» Hardware efficient architectures for Eigenvalue computation
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IPPS
1999
IEEE
15 years 2 months ago
An Efficient Implementation Method of Fractal Image Compression on Dynamically Reconfigurable Architecture
Abstract. This paper proposes a method for implementing fractal image compression on dynamically reconfigurable architecture. In the encoding of this compression, metric computatio...
Hidehisa Nagano, Akihiro Matsuura, Akira Nagoya
IPPS
2007
IEEE
15 years 4 months ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson
SIGGRAPH
1990
ACM
15 years 1 months ago
The accumulation buffer: hardware support for high-quality rendering
Paul Haeberli and Kurt Akeley SiliconGraphicsComputerSystems This paper describes a system architecture that supports realtime generation of complex images, efficient generation o...
Paul Haeberli, Kurt Akeley
ICMCS
2005
IEEE
109views Multimedia» more  ICMCS 2005»
15 years 3 months ago
An Efficient Architecture for Lifting-Based Forward and Inverse Discrete Wavelet Transform
In this research, an architecture that performs both forward and inverse lifting-based discrete wavelet transform is proposed. The proposed architecture reduces the hardware requi...
S. Mayilavelane Aroutchelvame, Kaamran Raahemifar
ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
15 years 6 months ago
Performance Efficiency of Context-Flow System-on-Chip Platform
Recent efforts in adapting computer networks into system-on-chip (SOC), or network-on-chip, present a setback to the traditional computer systems for the lack of effective program...
Rami Beidas, Jianwen Zhu