421 search results - page 2 / 85 » Hardware efficient architectures for Eigenvalue computation |
DAC
1997
ACM
13 years 10 months ago
1997
ACM
DAC
1996
ACM
13 years 10 months ago
1996
ACM
ARC
2012
Springer
12 years 2 months ago
2012
Springer
Iterative numerical algorithms with high memory bandwidth requirements but medium-size data sets (matrix size ∼ a few 100s) are highly appropriate for FPGA acceleration. This pap...
ACIVS
2008
Springer
13 years 8 months ago
2008
Springer
In this paper, we present a novel hardware architecture to achieve erosion and dilation with a large structuring element. We are proposing a modification of HGW algorithm with a bl...
HPCA
2007
IEEE
14 years 6 months ago
2007
IEEE