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HPCA
1998
IEEE
15 years 4 months ago
Address Translation Mechanisms In Network Interfaces
Good network hardware performance is often squandered by overheads for accessing the network interface (NI) within a host. NIs that support user-level messaging avoid frequent ope...
Ioannis Schoinas, Mark D. Hill
SIGMETRICS
2011
ACM
245views Hardware» more  SIGMETRICS 2011»
14 years 2 months ago
Record and transplay: partial checkpointing for replay debugging across heterogeneous systems
Software bugs that occur in production are often difficult to reproduce in the lab due to subtle differences in the application environment and nondeterminism. To address this pr...
Dinesh Subhraveti, Jason Nieh
DAC
2008
ACM
16 years 25 days ago
DVFS in loop accelerators using BLADES
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-t...
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott...
FPL
2005
Springer
96views Hardware» more  FPL 2005»
15 years 5 months ago
Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAs
Due to their layered approach, Networks-on-Chip (NoC) are a promising communication backbone in the field of heterogeneous dynamically reconfigurable systems. In this paper a fu...
Ronald Hecht, Stephan Kubisch, Andreas Herrholtz, ...
DAC
2004
ACM
16 years 24 days ago
An integrated hardware/software approach for run-time scratchpad management
An ever increasing number of dynamic interactive applications are implemented on portable consumer electronics. Designers depend largely on operating systems to map these applicat...
Francesco Poletti, Paul Marchal, David Atienza, Lu...