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FCCM
2009
IEEE
106views VLSI» more  FCCM 2009»
15 years 8 months ago
Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators
Modern use of FPGAs as hardware accelerators involves the partial reconfiguration of hardware resources as the application executes. In this paper, we present a polynomial time al...
Joon Edward Sim, Weng-Fai Wong, Jürgen Teich
ARC
2006
Springer
82views Hardware» more  ARC 2006»
15 years 7 months ago
Hardware and a Tool Chain for ADRES
Until recently, only a compiler and a high-level simulator of the reconfigurable architecture ADRES existed. This paper focuses on the problems that needed to be solved when moving...
Bjorn De Sutter, Bingfeng Mei, Andrei Bartic, Tom ...
126
Voted
EH
2004
IEEE
102views Hardware» more  EH 2004»
15 years 7 months ago
Design Space Issues for Intrinsic Evolvable Hardware
This paper discusses the problem of increased programming time for intrinsic evolvable hardware (EHW) as the complexity of the circuit grows. We develop equations for the size of ...
James Hereford, David A. Gwaltney
179
Voted
ENC
2004
IEEE
15 years 7 months ago
On the Hardware Design of an Elliptic Curve Cryptosystem
We present a hardware architecture for an Elliptic Curve Cryptography System performing the three basic cryptographic schemes: DH key generation, encryption and digital signature....
Miguel Morales-Sandoval, Claudia Feregrino Uribe
SC
2000
ACM
15 years 7 months ago
Hardware Prediction for Data Coherency of Scientific Codes on DSM
This paper proposes a hardware mechanism for reducing coherency overhead occurring in scientific computations within DSM systems. A first phase aims at detecting, in the address s...
Jean-Thomas Acquaviva, William Jalby