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DSN
2007
IEEE
15 years 8 months ago
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
Christopher LaFrieda, Engin Ipek, José F. M...
IEEEPACT
2007
IEEE
15 years 8 months ago
Architectural Support for the Stream Execution Model on General-Purpose Processors
There has recently been much interest in stream processing, both in industry (e.g., Cell, NVIDIA G80, ATI R580) and academia (e.g., Stanford Merrimac, MIT RAW), with stream progra...
Jayanth Gummaraju, Mattan Erez, Joel Coburn, Mende...
CLUSTER
2007
IEEE
15 years 8 months ago
Thermal-aware task scheduling for data centers through minimizing heat recirculation
— The thermal environment of data centers plays a significant role in affecting the energy efficiency and the reliability of data center operation. A dominant problem associate...
Qinghui Tang, Sandeep K. S. Gupta, Georgios Varsam...
GECCO
2007
Springer
183views Optimization» more  GECCO 2007»
15 years 8 months ago
Screening the parameters affecting heuristic performance
This research screens the tuning parameters of a combinatorial optimization heuristic. Specifically, it presents a Design of Experiments (DOE) approach that uses a Fractional Fac...
Enda Ridge, Daniel Kudenko
ICS
2007
Tsinghua U.
15 years 8 months ago
Performance driven data cache prefetching in a dynamic software optimization system
Software or hardware data cache prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued prefetches have to be monitored in order to maximi...
Jean Christophe Beyler, Philippe Clauss
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