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CODES
2003
IEEE
15 years 4 months ago
A codesigned on-chip logic minimizer
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...
Roman L. Lysecky, Frank Vahid
ICNP
2003
IEEE
15 years 4 months ago
Packet Classification Using Extended TCAMs
CAMs are the most popular practical method for implementing packet classification in high performance routers. Their principal drawbacks are high power consumption and inefficient...
Ed Spitznagel, David E. Taylor, Jonathan S. Turner
SLIP
2003
ACM
15 years 4 months ago
A hierarchical three-way interconnect architecture for hexagonal processors
The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wir...
Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Che...
DSOM
2003
Springer
15 years 4 months ago
Visual-Based Anomaly Detection for BGP Origin AS Change (OASC) Events
Instead of relying completely on machine intelligence in anomaly event analysis and correlation, in this paper, we take one step back and investigate the possibility of a human-int...
Soon Tee Teoh, Kwan-Liu Ma, Shyhtsun Felix Wu, Dan...
HIPC
2003
Springer
15 years 4 months ago
Performance Analysis of Blue Gene/L Using Parallel Discrete Event Simulation
High performance computers currently under construction, such as IBM’s Blue Gene/L, consisting of large numbers (64K) of low cost processing elements with relatively small local...
Ed Upchurch, Paul L. Springer, Maciej Brodowicz, S...