238 search results - page 9 / 48 » Hierarchical Interconnect Circuit Models |
SLIP
2009
ACM
15 years 6 months ago
2009
ACM
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
86
Voted
ICCAD
1997
IEEE
15 years 3 months ago
1997
IEEE
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
88
Voted
DAC
1995
ACM
15 years 3 months ago
1995
ACM
Abstract— Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and c...
DAC
2005
ACM
15 years 1 months ago
2005
ACM
Automated analog sizing is becoming an unavoidable solution for increasing analog design productivity. The complexity of typical analog SoC subsystems however calls for efficient ...
ISQED
2010
IEEE
15 years 4 months ago
2010
IEEE
A simulation-based feasibility study of an intra-chip wireless interconnect system is presented. The wireless interconnect system is modelled in a 250 nm standard complementary met...