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» Hierarchical Simulation of a Multiprocessor Architecture
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HPCA
1999
IEEE
15 years 3 months ago
Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors
Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not e...
Murthy Durbhakula, Vijay S. Pai, Sarita V. Adve
EUROPAR
2004
Springer
15 years 5 months ago
Modular On-chip Multiprocessor for Routing Applications
Abstract. Simulation platforms for network processing still have difficulties in finding a good compromise between speed and accuracy. This makes it difficult to identify the caus...
Saifeddine Berrayana, Etienne Faure, Daniela Geniu...
SIES
2009
IEEE
15 years 6 months ago
A modular fast simulation framework for stream-oriented MPSoC
—The performance estimation of complex multi-processor systems-on-chip (MPSoC) in a reasonable amount of time and with a good accuracy becomes more and more challenging due to th...
Kai Huang, Iuliana Bacivarov, Jun Liu, Wolfgang Ha...
IWOMP
2009
Springer
15 years 4 months ago
Dynamic Task and Data Placement over NUMA Architectures: An OpenMP Runtime Perspective
Abstract. Exploiting the full computational power of current hierarchical multiprocessor machines requires a very careful distribution of threads and data among the underlying non-...
François Broquedis, Nathalie Furmento, Bric...
DAC
1996
ACM
15 years 3 months ago
Symphony: A Simulation Backplane for Parallel Mixed-Mode Co-Simulation of VLSI Systems
In this paper we present an integrated simulation paradigm in which parallel mixed-mode co-simulation is accomplished by integrating sequential simulators in a software simulation ...
Antonio R. W. Todesco, Teresa H. Y. Meng