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ISCA
1997
IEEE
93views Hardware» more  ISCA 1997»
15 years 7 months ago
The Energy Efficiency of IRAM Architectures
Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more en...
Richard Fromm, Stylianos Perissakis, Neal Cardwell...
JCP
2008
118views more  JCP 2008»
15 years 4 months ago
Power-efficient Instruction Encoding Optimization for Various Architecture Classes
A huge application domain, in particular, wireless and handheld devices strongly requires flexible and powerefficient hardware with high performance. This can only be achieved with...
Diandian Zhang, Anupam Chattopadhyay, David Kammle...
JSA
2006
113views more  JSA 2006»
15 years 4 months ago
A power-efficient TCAM architecture for network forwarding tables
Stringent memory access and search speed requirements are two of the main bottlenecks in wire speed processing. Most viable search engines are implemented in content addressable m...
Taskin Koçak, Faysal Basci
FCCM
2011
IEEE
331views VLSI» more  FCCM 2011»
14 years 7 months ago
Synthesis of Platform Architectures from OpenCL Programs
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
Muhsen Owaida, Nikolaos Bellas, Konstantis Dalouka...
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
13 years 6 months ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar