Sciweavers

2852 search results - page 301 / 571
» High Performance Architectures and Compilers
Sort
View
DSN
2005
IEEE
15 years 10 months ago
Checking Array Bound Violation Using Segmentation Hardware
The ability to check memory references against their associated array/buffer bounds helps programmers to detect programming errors involving address overruns early on and thus avo...
Lap-Chung Lam, Tzi-cker Chiueh
EUROPAR
1999
Springer
15 years 8 months ago
Consequences of Modern Hardware Design for Numerical Simulations and Their Realization in FEAST
This paper deals with the influence of hardware aspects of modern computer architectures to the design of software for numerical simulations. We present performance tests for vari...
Christian Becker, Susanne Kilian, Stefan Turek
DAC
2006
ACM
16 years 5 months ago
An efficient and versatile scheduling algorithm based on SDC formulation
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
Jason Cong, Zhiru Zhang
DAC
2006
ACM
16 years 5 months ago
Exploiting forwarding to improve data bandwidth of instruction-set extensions
Application-specific instruction-set extensions (custom instructions) help embedded processors achieve higher performance. Most custom instructions offering significant performanc...
Ramkumar Jayaseelan, Haibin Liu, Tulika Mitra
IEEEPACT
2007
IEEE
15 years 10 months ago
Automatic Correction of Loop Transformations
Loop nest optimization is a combinatorial problem. Due to the growing complexity of modern architectures, it involves two increasingly difficult tasks: (1) analyzing the profita...
Nicolas Vasilache, Albert Cohen, Louis-Noël P...