2852 search results - page 6 / 571 » High Performance Architectures and Compilers |
135
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MICRO
2002
IEEE
15 years 9 months ago
2002
IEEE
Instruction cache aware compilation seeks to lay out a program in memory in such a way that cache conflicts between procedures are minimized. It does this through profile-driven...
129
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CLUSTER
2008
IEEE
15 years 11 months ago
2008
IEEE
—The industry is now in agreement that the future of architecture design lies in multiple cores. As a consequence, all computer systems today, from embedded devices to petascale ...
139
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LCPC
1999
Springer
15 years 9 months ago
1999
Springer
Poor performance on numerical codes has slowed the adoption of Java within the technical computing community. In this paper we describe a prototype array library and a research pr...
143
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SC
1992
ACM
15 years 8 months ago
1992
ACM
Exploiting parallelism at both the multiprocessor level and the instruction level is an e ective means for supercomputers to achieve high-performance. The amount of instruction-le...
151
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IPPS
2005
IEEE
15 years 10 months ago
2005
IEEE
“MegaProto” is a proof-of-concept prototype for our project “Mega-Scale Computing Based on Low-Power Technology and Workload Modeling”, implementing our key idea that a mi...