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ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
15 years 11 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
CF
2009
ACM
15 years 10 months ago
Space-and-time efficient garbage collectors for parallel systems
As multithreaded server applications and runtime systems prevail, garbage collection is becoming an essential feature to support high performance systems. The fundamental issue of...
Shaoshan Liu, Ligang Wang, Xiao-Feng Li, Jean-Luc ...
GLOBECOM
2007
IEEE
15 years 10 months ago
Initialization Techniques for Improved Convergence of LMS DFEs in Strong Interference Environments
— The least-mean square (LMS) decision-feedback equalizer (DFE) was previously shown [1], [2] to possess an extended convergence time in an interference limited environment. In [...
Arun Batra, James R. Zeidler, Aloysius A. Beex
ISCA
2007
IEEE
90views Hardware» more  ISCA 2007»
15 years 10 months ago
Transparent control independence (TCI)
AL-ZAWAWI, AHMED SAMI. Transparent Control Independence (TCI). (Under the direction of Dr. Eric Rotenberg). Superscalar architectures have been proposed that exploit control indep...
Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg...
CHES
2007
Springer
327views Cryptology» more  CHES 2007»
15 years 10 months ago
On the Power of Bitslice Implementation on Intel Core2 Processor
Abstract. This paper discusses the state-of-the-art fast software implementation of block ciphers on Intel’s new microprocessor Core2, particularly concentrating on “bitslice i...
Mitsuru Matsui, Junko Nakajima
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