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FASE
2007
Springer
15 years 7 months ago
A Family of Distributed Deadlock Avoidance Protocols and Their Reachable State Spaces
Abstract. We study resource management in distributed systems. Incorrect handling of resources may lead to deadlocks, missed deadlines, priority inversions, and other forms of inco...
César Sánchez, Henny B. Sipma, Zohar...
144
Voted
FPGA
2000
ACM
122views FPGA» more  FPGA 2000»
15 years 7 months ago
A reconfigurable multi-function computing cache architecture
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...
Huesung Kim, Arun K. Somani, Akhilesh Tyagi
ISCA
2000
IEEE
93views Hardware» more  ISCA 2000»
15 years 7 months ago
Reconfigurable caches and their application to media processing
High performance general-purpose processors are increasingly being used for a variety of application domains scienti c, engineering, databases, and more recently, media processing...
Parthasarathy Ranganathan, Sarita V. Adve, Norman ...
APBC
2004
122views Bioinformatics» more  APBC 2004»
15 years 5 months ago
Evolution of Relative Synonymous Codon Usage in Human Immunodeficiency Virus Type 1
Mutation in HIV-1 is extremely rapid, a consequence of a low-fidelity viral reverse transcription process. The envelope gene has been shown to accumulate substitutions at a rate o...
Peter L. Meintjes, Allen G. Rodrigo
140
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CLEF
2010
Springer
15 years 5 months ago
Automatic Prior Art Searching and Patent Encoding at CLEF-IP '10
In the intellectual property field two tasks are of high relevance: prior art searching and patent classification. Prior art search is fundamental for many strategic issues such as...
Douglas Teodoro, Julien Gobeill, Emilie Pasche, Di...
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