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ICS
2009
Tsinghua U.
15 years 6 months ago
Adagio: making DVS practical for complex HPC applications
Power and energy are first-order design constraints in high performance computing. Current research using dynamic voltage scaling (DVS) relies on trading increased execution time...
Barry Rountree, David K. Lowenthal, Bronis R. de S...
WMPI
2004
ACM
15 years 5 months ago
Scalable cache memory design for large-scale SMT architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
Muhamed F. Mudawar
CCGRID
2009
IEEE
15 years 6 months ago
BLAST Application with Data-Aware Desktop Grid Middleware
—There exists numerous Grid middleware to develop and execute programs on the computational Grid, but they still require intensive work from their users. BitDew is made to facili...
Haiwu He, Gilles Fedak, Bing Tang, Franck Cappello
IPPS
2007
IEEE
15 years 6 months ago
File Creation Strategies in a Distributed Metadata File System
As computing breaches petascale limits both in processor performance and storage capacity, the only way that current and future gains in performance can be achieved is by increasi...
Ananth Devulapalli, Pete Wyckoff
OTM
2007
Springer
15 years 6 months ago
Parallelizing Tableaux-Based Description Logic Reasoning
Practical scalability of Description Logic (DL) reasoning is an important premise for the adoption of OWL in a real-world setting. Many highly efficient optimizations for the DL ta...
Thorsten Liebig, Felix Müller