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JSA
2010
158views more  JSA 2010»
15 years 9 days ago
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...
SIGMETRICS
2009
ACM
157views Hardware» more  SIGMETRICS 2009»
16 years 22 hour ago
Delay tolerant bulk data transfers on the internet
Many emerging scientific and industrial applications require transferring multiple Tbytes of data on a daily basis. Examples include pushing scientific data from particle accele...
Nikolaos Laoutaris, Georgios Smaragdakis, Pablo Ro...
INFOCOM
2000
IEEE
15 years 10 months ago
Egress Admission Control
—Allocating resources for multimedia traffic flows with real-time performance requirements is an important challenge for future packet networks. However, in large-scale networks,...
Coskun Cetinkaya, Edward W. Knightly
PVM
1997
Springer
15 years 9 months ago
Embedding SCI into PVM
The extremely low latencies and high bandwidth results achievable with the Scalable Coherent Interface SCI at lowest level encourages its integration into existing Message Passin...
Markus Fischer, Jens Simon
BROADNETS
2004
IEEE
15 years 9 months ago
The Effects of the Sub-Carrier Grouping on Multi-Carrier Channel Aware Scheduling
Channel-aware scheduling and link adaptation (LA) methods are widely considered to be crucial for realizing high data rates in wireless networks. Multi-carrier systems that spread...
Fanchun Jin, Gokhan Sahin, Amrinder Arora, Hyeong-...