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FPL
2008
Springer
116views Hardware» more  FPL 2008»
14 years 11 months ago
NOC architecture design for multi-cluster chips
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...
Henrique C. Freitas, Philippe Olivier Alexandre Na...
BMCBI
2006
149views more  BMCBI 2006»
14 years 9 months ago
HeatMapper: powerful combined visualization of gene expression profile correlations, genotypes, phenotypes and sample characteri
Background: Accurate interpretation of data obtained by unsupervised analysis of large scale expression profiling studies is currently frequently performed by visually combining s...
Roel G. W. Verhaak, Mathijs A. Sanders, Maarten A....
BMCBI
2010
161views more  BMCBI 2010»
14 years 7 months ago
LTC: a novel algorithm to improve the efficiency of contig assembly for physical mapping in complex genomes
Background: Physical maps are the substrate of genome sequencing and map-based cloning and their construction relies on the accurate assembly of BAC clones into large contigs that...
Zeev Frenkel, Etienne Paux, David I. Mester, Cathe...
DFT
2006
IEEE
143views VLSI» more  DFT 2006»
15 years 3 months ago
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
Vijay K. Jain, Glenn H. Chapman
ICES
2005
Springer
177views Hardware» more  ICES 2005»
15 years 3 months ago
Evolving Hardware by Dynamically Reconfiguring Xilinx FPGAs
Evolvable Hardware arises as a promising solution for automatic digital synthesis of digital and analog circuits. During the last decade, a special interest has been focused on evo...
Andres Upegui, Eduardo Sanchez