154 search results - page 10 / 31 » High level cache simulation for heterogeneous multiprocessor... |
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
ISCA
2006
IEEE
15 years 3 months ago
2006
IEEE
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
77
Voted
DAC
2006
ACM
15 years 10 months ago
2006
ACM
ing models and HW-SW Interfaces Abstraction for Multi-Processor SoC Ahmed A. Jerraya TIMA Laboratory 46 Ave Felix Viallet 38031 Grenoble CEDEX, France +33476574759 Ahmed.Jerraya@im...
ICIP
1999
IEEE
15 years 11 months ago
1999
IEEE
A new chip-set for video display processing in a consumer television or set-top box is presented. Key aspect of the chip-set is a high flexibility and programmability of multi-win...
FPGA
2000
ACM
15 years 1 months ago
2000
ACM
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...