80 search results - page 3 / 16 » High level synthesis for reconfigurable datapath structures |
IPPS
2007
IEEE
14 years 17 days ago
2007
IEEE
ISSS
2002
IEEE
13 years 11 months ago
2002
IEEE
In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence,...
FPL
2005
Springer
13 years 11 months ago
2005
Springer
This paper describes novel data-path architecture for FPGA-based multimedia processors. The proposed circuit can adapt itself at run-time to different operations and data wordleng...
VTS
2007
IEEE
14 years 16 days ago
2007
IEEE
—As the complexity of the integrated circuits increases, they become more susceptible to manufacturing faults, decreasing the total process yield. Thus, it would be desirable to ...
VLSID
2003
IEEE
14 years 6 months ago
2003
IEEE
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...