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ARC
2008
Springer
104views Hardware» more  ARC 2008»
15 years 9 months ago
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
Frank Hannig, Holger Ruckdeschel, Hritam Dutta, J&...
IPPS
2007
IEEE
16 years 1 months ago
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao
GECCO
2007
Springer
179views Optimization» more  GECCO 2007»
16 years 1 months ago
A destructive evolutionary process: a pilot implementation
This paper describes the application of evolutionary search to the problem of Flash memory wear-out. The operating parameters of Flash memory are notoriously difficult to determin...
Joe Sullivan, Conor Ryan
CCGRID
2007
IEEE
16 years 1 months ago
CyberBridges A Model Collaboration Infrastructure for e-Science
The “CyberBridges” pilot project is an innovative model for creating a new generation of scientists and engineers who are capable of fully integrating cyberinfrastructure into...
Heidi L. Alvarez, David C. Chatfield, Donald A. Co...
EGH
2010
Springer
15 years 5 months ago
Hardware implementation of micropolygon rasterization with motion and defocus blur
Current GPUs rasterize micropolygons (polygons approximately one pixel in size) inefficiently. Additionally, they do not natively support triangle rasterization with jittered samp...
J. S. Brunhaver, Kayvon Fatahalian, Pat Hanrahan