116 search results - page 10 / 24 » High throughput architecture for packet classification using... |
92
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JSA
2010
14 years 4 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
104
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FPGA
2009
ACM
15 years 2 months ago
2009
ACM
This paper presents a new architecture for time-to-digital conversion enabling a time resolution of 17ps over a range of 50ns with a conversion rate of 20MS/s. The proposed archit...
PERCOM
2007
ACM
15 years 9 months ago
2007
ACM
To enhance the per node throughput, mesh nodes in wireless mesh networks can be equipped with multiple network interfaces (NIC). In this paper, we propose a new multi-interface equ...
CHES
2007
Springer
15 years 3 months ago
2007
Springer
Abstract. This paper presents a design-space exploration of the Galois/Counter Mode (GCM) algorithm with Advanced Encryption Standard (AES) as underlying block cipher for high thro...
INFOCOM
2005
IEEE
15 years 3 months ago
2005
IEEE
— The advent of packet networks has motivated many researchers to study the performance of networks of queues in the last decade or two. However, most of the previous work assume...