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GLOBECOM
2009
IEEE
13 years 10 months ago
Energy-Efficient Multi-Pipeline Architecture for Terabit Packet Classification
Energy efficiency has become a critical concern in designing high speed packet classification engines for next generation routers. Although TCAM-based solutions can provide high th...
Weirong Jiang, Viktor K. Prasanna
FCCM
2009
IEEE
123views VLSI» more  FCCM 2009»
13 years 10 months ago
Scalable High Throughput and Power Efficient IP-Lookup on FPGA
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...
Hoang Le, Viktor K. Prasanna
FCCM
2004
IEEE
141views VLSI» more  FCCM 2004»
13 years 10 months ago
Deep Packet Filter with Dedicated Logic and Read Only Memories
Searching for multiple string patterns in a stream of data is a computationally expensive task. The speed of the search pattern module determines the overall performance of deep p...
Young H. Cho, William H. Mangione-Smith
IPPS
2008
IEEE
14 years 20 days ago
Energy efficient packet classification hardware accelerator
Packet classification is an important function in a router’s line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classifi...
Alan Kennedy, Xiaojun Wang, Bin Liu
CLEIEJ
2010
13 years 3 months ago
High Throughput and Low Cost Architecture for the Forward Quantization of the H.264/AVC Video Compression Standard
This work presents a dedicated hardware design for the Forward Quantization Module (Q module) of the H.264/AVC Video Coding Standard, using optimized multipliers. The goal of this...
Felipe Sampaio, Daniel Palomino, Robson Dornelles,...