1024 search results - page 38 / 205 » High-Level Execution Time Analysis |
148
Voted
IPPS
2006
IEEE
15 years 9 months ago
2006
IEEE
Design space exploration of multiprocessors on chip requires both automatic performance analysis techniques and efficient multiprocessors configuration performance evaluation. Pr...
129
Voted
OTM
2004
Springer
15 years 8 months ago
2004
Springer
Cache memories are mandatory to bridge the growing gap between CPU speed and main memory access time. Standard cache organizations improve the average execution time but are diffi...
137
Voted
HPDC
2006
IEEE
15 years 9 months ago
2006
IEEE
Consider a workload in which massively parallel tasks that require large resource pools are interleaved with short tasks that require fast response but consume fewer resources. We...
121
Voted
EMSOFT
2005
Springer
15 years 9 months ago
2005
Springer
Abstract— This paper explores the problem of efficiently ordering interprocessor communication operations in both statically and dynamically-scheduled multiprocessors for iterat...
103
Voted
IPPS
2000
IEEE
15 years 8 months ago
2000
IEEE
In this paper, we present a method to estimate the number of reconfiguration steps that a time-constrained algorithm can accommodate. This analysis demonstrates how one would attac...