173 search results - page 4 / 35 » High-Level Power Modeling, Estimation, and Optimization |
ASPDAC
2004
ACM
15 years 1 months ago
2004
ACM
- Each year tens of billions of Dollars are wasted by the microelectronics industry because of missed deadlines and delayed design projects. These delays are partially due to desig...
DAC
1997
ACM
15 years 1 months ago
1997
ACM
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
105
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CODES
2004
IEEE
15 years 1 months ago
2004
IEEE
There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area i...
109
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VLSID
2005
IEEE
15 years 10 months ago
2005
IEEE
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
ISLPED
2003
ACM
15 years 2 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...