181 search results - page 11 / 37 » High-level area and power estimation for VLSI circuits |
ISSS
2002
IEEE
15 years 2 months ago
2002
IEEE
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
GLVLSI
2003
IEEE
15 years 2 months ago
2003
IEEE
—Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effectiv...
VLSID
2005
IEEE
15 years 10 months ago
2005
IEEE
An accurate and efficient stacking effect macro-model for leakage power in sub-100nm circuits is presented in this paper. Leakage power, including subthreshold leakage power and ga...
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...
97
Voted
ICTAI
1997
IEEE
15 years 1 months ago
1997
IEEE
This paper proposes an optimization algorithm for reducing the power dissipation in a sequential circuit. The encoding of the different states in a Finite State Machine is modifie...