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» High-level power estimation with interconnect effects
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ICCAD
2004
IEEE
88views Hardware» more  ICCAD 2004»
15 years 7 months ago
Interconnect lifetime prediction under dynamic stress for reliability-aware design
Thermal effects are becoming a limiting factor in highperformance circuit design due to the strong temperaturedependence of leakage power, circuit performance, IC package cost and...
Zhijian Lu, Wei Huang, John Lach, Mircea R. Stan, ...
ICCAD
2003
IEEE
120views Hardware» more  ICCAD 2003»
15 years 7 months ago
RTL Power Optimization with Gate-Level Accuracy
Traditional RTL power optimization techniques commit transformations at the RTL based on the estimation of area, delay and power. However, because of inadequate power and delay in...
Qi Wang, Sumit Roy
NOCS
2009
IEEE
15 years 4 months ago
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
Anh T. Tran, Dean Truong, Bevan M. Baas
CODES
2004
IEEE
15 years 1 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
DPHOTO
2010
208views Hardware» more  DPHOTO 2010»
14 years 11 months ago
A signature analysis based method for elliptical shape
The high level context image analysis regards many fields as face recognition, smile detection, automatic red eye removal, iris recognition, fingerprint verification, etc. Techniq...
Ivana Guarneri, Mirko Guarnera, Giuseppe Messina, ...