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» High-level power estimation
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93
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DAC
1999
ACM
15 years 5 months ago
A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs
In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a oorplan-based power and clock distribution meth...
Joon-Seo Yim, Seong-Ok Bae, Chong-Min Kyung
ICDM
2007
IEEE
131views Data Mining» more  ICDM 2007»
15 years 4 months ago
Predicting and Optimizing Classifier Utility with the Power Law
When data collection is costly and/or takes a significant amount of time, an early prediction of the classifier performance is extremely important for the design of the data minin...
Mark Last
90
Voted
JSAC
2006
91views more  JSAC 2006»
15 years 23 days ago
Innovative model for time-varying power line communication channel response evaluation
Abstract--This work presents a channel model for the broadband characterization of power lines in presence of time variation of the loads. The model is characterized by taking into...
Sami Barmada, Antonino Musolino, Marco Raugi
CC
2002
Springer
131views System Software» more  CC 2002»
15 years 20 days ago
Global Variable Promotion: Using Registers to Reduce Cache Power Dissipation
Global variable promotion, i.e. allocating unaliased globals to registers, can significantly reduce the number of memory operations. This results in reduced cache activity and less...
Andrea G. M. Cilio, Henk Corporaal
105
Voted
ASPDAC
2010
ACM
137views Hardware» more  ASPDAC 2010»
14 years 11 months ago
Improved on-chip router analytical power and area modeling
Over the course of this decade, uniprocessor chips have given way to multi-core chips which have become the primary building blocks of today's computer systems. The presence o...
Andrew B. Kahng, Bill Lin, Kambiz Samadi