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» High-level power estimation
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HOST
2008
IEEE
15 years 7 months ago
Slicing Up a Perfect Hardware Masking Scheme
—Masking is a side-channel countermeasure that randomizes side-channel leakage, such as the power dissipation of a circuit. Masking is only effective on the condition that the in...
Zhimin Chen, Patrick Schaumont
IPPS
2006
IEEE
15 years 6 months ago
Selection of instruction set extensions for an FPGA embedded processor core
A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The i...
Brian F. Veale, John K. Antonio, Monte P. Tull, S....
JCP
2006
110views more  JCP 2006»
15 years 20 days ago
Gateway Selection Review in Ad hoc Networks
The nature of wireless mobile ad hoc networks depend on batteries or other fatiguing means for their energy. A limited energy capacity may be the most significant performance const...
Tarek Sheltami
80
Voted
IPPS
2007
IEEE
15 years 7 months ago
STAMP: A Universal Algorithmic Model for Next-Generation Multithreaded Machines and Systems
We propose a generic algorithmic model called STAMP (Synchronous, Transactional, and Asynchronous MultiProcessing) as a universal performance and power complexity model for multit...
Michel Dubois, Hyunyoung Lee, Lan Lin
DATE
1999
IEEE
112views Hardware» more  DATE 1999»
15 years 5 months ago
Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach
Estimating switching activity is a crucial step in optimizing circuits for low power. In this paper, a fast gate level switching activity estimator for combinational circuits will...
Markus Bühler, Matthias Papesch, K. Kapp, Utz...