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» High-precision interconnect analysis
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IPPS
2007
IEEE
15 years 8 months ago
Performance Modelling of Necklace Hypercubes
The necklace hypercube has recently been introduced as an attractive alternative to the well-known hypercube. Previous research on this network topology has mainly focused on topo...
Sina Meraji, Hamid Sarbazi-Azad, Ahmad Patooghy
DSN
2006
IEEE
15 years 8 months ago
Exploring Fault-Tolerant Network-on-Chip Architectures
The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are ...
Dongkook Park, Chrysostomos Nicopoulos, Jongman Ki...
FPL
2005
Springer
112views Hardware» more  FPL 2005»
15 years 7 months ago
Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement
Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate ...
Anthony J. Yu, Guy G. Lemieux
WCRE
1996
IEEE
15 years 6 months ago
Finding Reusable Software Components in Large Systems
The extraction of reusable software components from existing systems is an attractive idea. The goal of the work in this paper is not to extract a component automatically, but to ...
James M. Neighbors
ANCS
2007
ACM
15 years 6 months ago
Experimental evaluation of a coarse-grained switch scheduler
Modern high performance routers rely on sophisticated interconnection networks to meet ever increasing demands on capacity. Previous studies have used a combination of analysis an...
Charlie Wiseman, Jonathan S. Turner, Ken Wong, Bra...