43 search results - page 8 / 9 » Hybrid Cache Architecture for High Speed Packet Processing |
117
Voted
ICPP
1997
IEEE
15 years 7 months ago
1997
IEEE
Most of recent research on distributed shared memory (DSM)systems have focused on either careful design of node controllersor cache coherenceprotocols. Whileevaluating these desig...
173
Voted
IPPS
2007
IEEE
15 years 10 months ago
2007
IEEE
Search-based graph queries, such as finding short paths and isomorphic subgraphs, are dominated by memory latency. If input graphs can be partitioned appropriately, large cluster...
208
Voted
SIGCOMM
1995
ACM
15 years 7 months ago
1995
ACM
MD5 is an authentication algorithm proposed as the required implementation of the authentication option in IPv6. This paper presents an analysis of the speed at which MD5 can be i...
131
Voted
CF
2004
ACM
15 years 9 months ago
2004
ACM
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
146
Voted
MICRO
2008
IEEE
15 years 10 months ago
2008
IEEE
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communicat...