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» ILP-based optimization of sequential circuits for low power
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ICCAD
2006
IEEE
124views Hardware» more  ICCAD 2006»
15 years 6 months ago
Simultaneous power and thermal integrity driven via stapling in 3D ICs
The existing work on via-stapling in 3D integrated circuits optimizes power and thermal integrity separately and uses steadystate thermal analysis. This paper presents the first ...
Hao Yu, Joanna Ho, Lei He
ISCAS
2006
IEEE
119views Hardware» more  ISCAS 2006»
15 years 3 months ago
Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...
Saraju P. Mohanty, Elias Kougianos, Ramakrishna Ve...
EVOW
2000
Springer
15 years 1 months ago
Prediction of Power Requirements for High-Speed Circuits
Modern VLSI design methodologies and manufacturing technologies are making circuits increasingly fast. The quest for higher circuit performance and integration density stems from f...
Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Re...
DAC
2009
ACM
15 years 2 months ago
GPU-based parallelization for fast circuit optimization
The progress of GPU (Graphics Processing Unit) technology opens a new avenue for boosting computing power. This work is an attempt to exploit GPU for accelerating VLSI circuit opt...
Yifang Liu, Jiang Hu
DATE
2008
IEEE
131views Hardware» more  DATE 2008»
15 years 3 months ago
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints
Sleep transistor insertion is one of today’s most promising and widely adopted solutions for controlling stand-by leakage power in nanometer circuits. Although single-cycle powe...
Andrea Calimera, Luca Benini, Enrico Macii