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» IPR: An Integrated Placement and Routing Algorithm
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106
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DAC
2004
ACM
16 years 17 days ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
FPGA
2004
ACM
145views FPGA» more  FPGA 2004»
15 years 5 months ago
Exploration of pipelined FPGA interconnect structures
In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of regist...
Akshay Sharma, Katherine Compton, Carl Ebeling, Sc...
105
Voted
SLIP
2003
ACM
15 years 4 months ago
Perimeter-degree: a priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement
In this paper, we describe an accurate metric (perimeter-degree) for measuring interconnection complexity and effective use of it for controlling congestion in a multilevel framew...
Navaratnasothie Selvakkumaran, Phiroze N. Parakh, ...
FPGA
2009
ACM
233views FPGA» more  FPGA 2009»
15 years 6 months ago
FPCNA: a field programmable carbon nanotube array
Carbon nanotubes (CNTs), with their unique electronic properties, are promising materials for building nanoscale circuits. In this paper, we present a new CNT-based FPGA architect...
Chen Dong, Scott Chilstedt, Deming Chen
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
15 years 4 months ago
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
Cheng-Kok Koh, Patrick H. Madden