111 search results - page 21 / 23 » IPR: An Integrated Placement and Routing Algorithm |
DAC
2009
ACM
16 years 18 days ago
2009
ACM
Metal-only ECO realizes the last-minute design changes by revising the photomasks of metal layers only. This task is challenging because the pre-injected spare cells are limited b...
VLSID
2002
IEEE
15 years 12 months ago
2002
IEEE
One of the major roadblocks in reduction of library generation cycle time is the layout generation phase. The two methods of doing automatic layout generation are synthesis and mig...
SLIP
2009
ACM
15 years 6 months ago
2009
ACM
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
GLVLSI
2006
IEEE
15 years 5 months ago
2006
IEEE
In modern IC design, the number of long on-chip wires has been growing rapidly because of the increasing circuit complexity. Interconnect delay has dominated over gate delay as te...
ASPDAC
2008
ACM
15 years 1 months ago
2008
ACM
ACT Benchmarks are an immensely useful tool in performing research since they allow for rapid and clear comparison between different approaches to solving CAD problems. Recent expe...