111 search results - page 4 / 23 » IPR: An Integrated Placement and Routing Algorithm |
DAC
2007
ACM
16 years 17 days ago
2007
ACM
In this paper, we present a new multi-packing tree (MP-tree) representation for macro placement to handle mixed-size designs. Based on binary trees, the MP-tree is very efficient,...
DATE
2003
IEEE
15 years 4 months ago
2003
IEEE
– Floorplanning large designs with many hard macros and IP blocks of various sizes is becoming an increasingly important and challenging problem. This paper presents a global flo...
103
click to vote
DAC
2012
ACM
13 years 2 months ago
2012
ACM
In this paper, we propose two methods used in 3D IC placement that effectively exploit the die-to-die thermal coupling in the stack. First, TSVs are spread on each die to reduce t...
DATE
2005
IEEE
15 years 5 months ago
2005
IEEE
In this paper, we present an experimental integrated platform for the research, development and evaluation of new VLSI back-end algorithms and design flows. Interconnect scaling ...
117
click to vote
GLVLSI
2007
IEEE
15 years 6 months ago
2007
IEEE
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...