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» IPR: An Integrated Placement and Routing Algorithm
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ISPD
2003
ACM
92views Hardware» more  ISPD 2003»
15 years 4 months ago
Benchmarking for large-scale placement and beyond
Over the last five years the VLSI Placement community achieved great strides in the understanding of placement problems, developed new high-performance algorithms, and achieved i...
Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov...
FPGA
2009
ACM
209views FPGA» more  FPGA 2009»
15 years 6 months ago
SPR: an architecture-adaptive CGRA mapping tool
In this paper we present SPR, a new architecture-adaptive mapping tool for use with Coarse-Grained Reconfigurable Architectures (CGRAs). It combines a VLIW style scheduler and FP...
Stephen Friedman, Allan Carroll, Brian Van Essen, ...
DAC
2009
ACM
16 years 18 days ago
Flip-chip routing with unified area-I/O pad assignments for package-board co-design
In this paper, we present a novel flip-chip routing algorithm for package-board co-design. Unlike the previous works that can consider only either free- or pre-assignment routing,...
Jia-Wei Fang, Martin D. F. Wong, Yao-Wen Chang
DAC
2009
ACM
16 years 18 days ago
Handling complexities in modern large-scale mixed-size placement
In this paper, we propose an effective algorithm flow to handle largescale mixed-size placement. The basic idea is to use floorplanning to guide the placement of objects at the gl...
Jackey Z. Yan, Natarajan Viswanathan, Chris Chu
FPGA
2005
ACM
80views FPGA» more  FPGA 2005»
15 years 5 months ago
Simultaneous timing-driven placement and duplication
Logic duplication is an effective method for improving circuit performance. In this paper we present an algorithm named SPD that performs simultaneous placement and duplication to...
Gang Chen, Jason Cong