Sciweavers

124 search results - page 8 / 25
» IXM2: A Parallel Associative Processor
Sort
View
132
Voted
IPPS
2007
IEEE
15 years 10 months ago
A Key-based Adaptive Transactional Memory Executor
Software transactional memory systems enable a programmer to easily write concurrent data structures such as lists, trees, hashtables, and graphs, where non-conflicting operation...
Tongxin Bai, Xipeng Shen, Chengliang Zhang, Willia...
111
Voted
ICS
2000
Tsinghua U.
15 years 7 months ago
A low-complexity issue logic
One of the main concerns in today's processor design is the issue logic. Instruction-level parallelism is usually favored by an out-of-order issue mechanism where instruction...
Ramon Canal, Antonio González
128
Voted
IPPS
2009
IEEE
15 years 10 months ago
A component-based framework for the Cell Broadband Engine
With the increasing trend of microprocessor manufacturers to rely on parallelism to increase their products’ performance, there is an associated increasing need for simple techn...
Timothy D. R. Hartley, Ümit V. Çataly&...
CASES
2000
ACM
15 years 7 months ago
Flexible instruction processors
This paper introduces the notion of a Flexible Instruction Processor (FIP) for systematic customisation of instruction processor design and implementation. The features of our app...
Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung
152
Voted
ANSS
2002
IEEE
15 years 8 months ago
Gang Scheduling Performance on a Cluster of Non-Dedicated Workstations
Clusters of workstations have emerged as a costeffective solution to high performance computing problem. To take advantage of any opportunities, however, effective scheduling tech...
Helen D. Karatza