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ISLPED
2006
ACM
105views Hardware» more  ISLPED 2006»
14 years 5 days ago
Reducing power through compiler-directed barrier synchronization elimination
Interprocessor synchronization, while extremely important for ensuring execution correctness, can be very costly in terms of both power and performance overheads. Unfortunately, m...
Mahmut T. Kandemir, Seung Woo Son
CODES
2011
IEEE
12 years 6 months ago
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
Garo Bournoutian, Alex Orailoglu
HPCA
2004
IEEE
14 years 6 months ago
The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors
Much research has been devoted to making microprocessors energy-efficient. However, little attention has been paid to multiprocessor environments where, due to the co-operative na...
Jian Li, José F. Martínez, Michael C...
MOBILIGHT
2010
13 years 4 months ago
A Framework for the Design Space Exploration of Software-Defined Radio Applications
Abstract. This paper describes a framework for the design space exploration of resource-efficient software-defined radio architectures. This design space exploration is based on a ...
Thorsten Jungeblut, Ralf Dreesen, Mario Porrmann, ...
IEEEPACT
2006
IEEE
14 years 8 days ago
Adaptive reorder buffers for SMT processors
In SMT processors, the complex interplay between private and shared datapath resources needs to be considered in order to realize the full performance potential. In this paper, we...
Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev