801 search results - page 76 / 161 » Implementation and Use of Transactional Memory with Dynamic ... |
FPL
2008
Springer
14 years 11 months ago
2008
Springer
In multi-context Dynamically Reconfigurable Processor Array (DRPA), the required number of contexts is often increased by those with low resource usage. In order to execute such c...
105
click to vote
CLUSTER
2008
IEEE
14 years 11 months ago
2008
IEEE
Efficient intra-node shared memory communication is important for High Performance Computing (HPC), especially with the emergence of multi-core architectures. As clusters continue ...
ICPP
1993
IEEE
15 years 1 months ago
1993
IEEE
SIMD or vector computers and collection-oriented languages, like C , are designed to perform the same computation on each data item or on just a subset of the data. Subsets of pro...
NOCS
2007
IEEE
15 years 4 months ago
2007
IEEE
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
ESANN
2003
14 years 11 months ago
2003
The paper presents a method for times series prediction using a local dynamic modeling based on a three step process. In the first step the input data is embedded in a reconstruct...