1675 search results - page 215 / 335 » Implementing Data Cubes Efficiently |
135
Voted
APCSAC
2001
IEEE
15 years 7 months ago
2001
IEEE
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
109
click to vote
EUROPAR
2000
Springer
15 years 7 months ago
2000
Springer
With the increasing processing power, the latency of the memory hierarchy becomes the stumbling block of many modern computer architectures. In order to speed-up the calculations, ...
139
click to vote
CPM
2009
Springer
15 years 7 months ago
2009
Springer
In this paper we present in detail a new efficient linear time and space suffix array construction algorithm(SACA), called the D-CriticalSubstring algorithm. The algorithm is built...
117
Voted
FAST
2008
15 years 5 months ago
2008
Operating system memory managers fail to consider the population of read versus write pages in the buffer pool or outstanding I/O requests when writing dirty pages to disk or netw...
134
click to vote
ANCS
2008
ACM
15 years 5 months ago
2008
ACM
Computer networks require increasingly complex packet processing in the data path to adapt to new functionality requirements. To meet performance demands, packet processing system...