Sciweavers

49 search results - page 4 / 10
» Implementing LDPC Decoding on Network-on-Chip
Sort
View
ISCAS
2006
IEEE
109views Hardware» more  ISCAS 2006»
15 years 5 months ago
A bit-serial approximate min-sum LDPC decoder and FPGA implementation
Ahmad Darabiha, Anthony Chan Carusone, Frank R. Ks...
JSAC
2008
124views more  JSAC 2008»
14 years 11 months ago
Design Tradeoffs and Hardware Architecture for Real-Time Iterative MIMO Detection using Sphere Decoding and LDPC Coding
Abstract-- We explore the performance and hardware complexity tradeoffs associated with performing iterative multipleinput multiple-output (MIMO) detection using a sphere decoder a...
Hyungjin Kim, Dong-U Lee, John D. Villasenor
SIPS
2006
IEEE
15 years 5 months ago
Partly Parallel Overlapped Sum-Product Decoder Architectures for Quasi-Cyclic LDPC Codes
Abstract— In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization effi...
Ning Chen, Yongmei Dai, Zhiyuan Yan
VLSID
2006
IEEE
158views VLSI» more  VLSID 2006»
15 years 5 months ago
Programmable LDPC Decoder Based on the Bubble-Sort Algorithm
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardw...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
ICC
2007
IEEE
15 years 6 months ago
Low-Complexity, Low-Memory EMS Algorithm for Non-Binary LDPC Codes
— In this paper, we propose a new implementation of the EMS decoder for non binary LDPC codes presented in [7]. A particularity of the new algorithm is that it takes into account...
Adrian Voicila, David Declercq, François Ve...