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VLSI
2010
Springer
15 years 25 days ago
A design workflow for dynamically reconfigurable multi-FPGA systems
Multi-FPGA systems (MFS's) represent a promising technology for various applications, such as the implementation of supercomputers and parallel and computational intensive emu...
Alessandro Panella, Marco D. Santambrogio, Frances...
192
Voted
ISCAS
2011
IEEE
261views Hardware» more  ISCAS 2011»
14 years 9 months ago
Hardware synchronization for embedded multi-core processors
Abstract— Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers shou...
Christian Stoif, Martin Schoeberl, Benito Liccardi...
INFOCOM
2012
IEEE
13 years 8 months ago
Block permutations in Boolean Space to minimize TCAM for packet classification
Packet classification is one of the major challenges in designing high-speed routers and firewalls as it involves sophisticated multi-dimensional searching. Ternary Content Address...
Rihua Wei, Yang Xu, H. Jonathan Chao
ICPP
2009
IEEE
16 years 24 days ago
Speeding Up Distributed MapReduce Applications Using Hardware Accelerators
—In an attempt to increase the performance/cost ratio, large compute clusters are becoming heterogeneous at multiple levels: from asymmetric processors, to different system archi...
Yolanda Becerra, Vicenç Beltran, David Carr...
213
Voted
PVM
1997
Springer
15 years 10 months ago
Embedding SCI into PVM
The extremely low latencies and high bandwidth results achievable with the Scalable Coherent Interface SCI at lowest level encourages its integration into existing Message Passin...
Markus Fischer, Jens Simon