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» Implementing a STARI chip
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FPL
2006
Springer
242views Hardware» more  FPL 2006»
15 years 1 months ago
TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
Manuel Saldaña, Paul Chow
CVIU
2010
115views more  CVIU 2010»
14 years 9 months ago
A modified model for the Lobula Giant Movement Detector and its FPGA implementation
Bio-inspired vision sensors are particularly appropriate candidates for navigation of vehicles or mobile robots due to their computational simplicity, allowing compact hardware im...
Hongying Meng, Kofi Appiah, Shigang Yue, Andrew Hu...
DATE
2008
IEEE
113views Hardware» more  DATE 2008»
15 years 4 months ago
Compositional, dynamic cache management for embedded chip multiprocessors
This paper proposes a dynamic cache repartitioning technique that enhances compositionality on platforms executing media applications with multiple utilization scenarios. The repa...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
IEEEPACT
2008
IEEE
15 years 4 months ago
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor
Moore’s Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneo...
Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aa...
EMSOFT
2005
Springer
15 years 3 months ago
Optimizing inter-processor data locality on embedded chip multiprocessors
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
Guilin Chen, Mahmut T. Kandemir