Sciweavers

857 search results - page 71 / 172
» Implementing a STARI chip
Sort
View
ETS
2007
IEEE
105views Hardware» more  ETS 2007»
15 years 4 months ago
Communication-Centric SoC Debug Using Transactions
— The growth in System-on-Chip complexity puts pressure on system verification. Due to limitations in the pre-silicon verification process, errors in hardware and software slip...
Bart Vermeulen, Kees Goossens, Remco van Steeden, ...
ISQED
2005
IEEE
76views Hardware» more  ISQED 2005»
15 years 3 months ago
Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers
Multi-project wafer having several chips placed on the same reticle to lower mask cost is key to low-volume IC fabrication. In this paper1 , we proposed two MILP models for simult...
Meng-Chiou Wu, Rung-Bin Lin
IPPS
2000
IEEE
15 years 2 months ago
MAJC-5200: A High Performance Microprocessor for Multimedia Computing
The newly introduced Microprocessor Architecture for Java Computing MAJC supports parallelism in a hierarchy of levels: multiprocessors on chip,vertical micro threading, instruct...
Subramania Sudharsanan
KES
1998
Springer
15 years 2 months ago
Insect vision based motion detection
The architectural and circuit design aspects of a mixed analog/digital very large scale integration (VLSI) motion detection chip based on models of the insect visual system are des...
X. T. Nguyen
VEE
2012
ACM
234views Virtualization» more  VEE 2012»
13 years 5 months ago
REEact: a customizable virtual execution manager for multicore platforms
With the shift to many-core chip multiprocessors (CMPs), a critical issue is how to effectively coordinate and manage the execution of applications and hardware resources to overc...
Wei Wang, Tanima Dey, Ryan W. Moore, Mahmut Aktaso...