857 search results - page 75 / 172 » Implementing a STARI chip |
IPPS
2007
IEEE
15 years 4 months ago
2007
IEEE
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
Abstract- This paper describes the implementation of an areaefficient and protected user memory-mapped network interface, the pbuf (Parcel Buffer), for the Data IntensiVe Architect...
100
click to vote
DATE
1998
IEEE
15 years 2 months ago
1998
IEEE
This paper presents a VLSI Architecture to implement the forward and inverse 2-D Discrete Wavelet Transform (FDWT/IDWT), to compress medical images for storage and retrieval. Loss...
VLSID
2006
IEEE
15 years 10 months ago
2006
IEEE
In this paper we present a high-performance, high throughput, and area efficient architecture for the VLSI implementation of the AES algorithm. The subkeys, required for each round...
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
In this paper, we use the generalized binary de Bruijn (GBDB) graph as a scalable and efficient network topology for an on-chip communication network. Using just two-layer wiring,...