Sciweavers

581 search results - page 16 / 117
» Implementing the Best Processor Cores
Sort
View
ISCA
2012
IEEE
244views Hardware» more  ISCA 2012»
13 years 2 months ago
Scheduling heterogeneous multi-cores through performance impact estimation (PIE)
Single-ISA heterogeneous multi-core processors are typically composed of small (e.g., in-order) power-efficient cores and big (e.g., out-of-order) high-performance cores. The eff...
Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout...
CSREAESA
2009
15 years 25 days ago
Embedded Processor Based Fault Injection and SEU Emulation for FPGAs
Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip...
Bradley F. Dutton, Mustafa Ali, Charles E. Stroud,...
IPPS
2006
IEEE
15 years 5 months ago
Compatible phase co-scheduling on a CMP of multi-threaded processors
The industry is rapidly moving towards the adoption of Chip Multi-Processors (CMPs) of Simultaneous MultiThreaded (SMT) cores for general purpose systems. The most prominent use o...
Ali El-Moursy, R. Garg, David H. Albonesi, Sandhya...
LATINCRYPT
2010
14 years 10 months ago
New Software Speed Records for Cryptographic Pairings
Abstract. This paper presents new software speed records for the computation of cryptographic pairings. More specifically, we present details of an implementation which computes t...
Michael Naehrig, Ruben Niederhagen, Peter Schwabe
DAMON
2006
Springer
15 years 3 months ago
Realizing parallelism in database operations: insights from a massively multithreaded architecture
A new trend in processor design is increased on-chip support for multithreading in the form of both chip multiprocessors and simultaneous multithreading. Recent research in databa...
John Cieslewicz, Jonathan W. Berry, Bruce Hendrick...